Secure Processor Version 1 Increases Security Against Cyber Attacks Published Feb. 4, 2013 By John Rooks Information ROME, New York -- The newly released, government-owned Secure Processor was designed with unique cyber security hardware and software features for resistance and resiliency against cyber attacks. Version 1 was designed for IBM's 65nm 10LPe manufacturing process. The chip has four processors, each of which have an 8 KByte cache, 2 MBytes of on-chip Static Random Access Memory, and a 64-bit wide mobile Double Data Rate memory interface. The four processors, two 10 Gibabit Ethernet ports, and a Read-Only Memory interface are interconnected by a 7-port crossbar switch. The chip design is 11 mm x 14 mm, and has 824 area array Input/Outputs.